1. Field of the Invention
The present invention relates to a test circuit for testing the operation of circuit blocks that are controlled by microinstructions.
2. Description of the Prior Art
In a microprocessor, circuit blocks such as ALUs (Arithmetic Logic Units), shifters and register files are connected to each other through an internal bus and controlled with microinstructions. To efficiently test the operation of these circuit blocks from the outside of an LSI chip that contains the circuit blocks, a test circuit such as the one shown in FIG. 1 is conventionally used.
In FIG. 1, a macroblock 1 is a circuit block such as an ALU and a shifter that receives data from an internal bus 2 of a microprocessor via latch circuits 3 (LAT1 and LAT2). A macroblock 4 such as a register file directly receives data from the internal bus 2. Signals of the macroblocks 1 and 4 are outputted to the internal bus 2 via output buffers 5. The internal bus 2 is connected to a data pin 7 and an address pin 8 through I/O buffers 6. Data are inputted to and outputted from the circuit blocks 1 and 4 via the pins 7 and 8.
The macroblocks 1 and 4 are connected to circuits 9 (hereinafter called the TFF circuits). As will be explained later with reference to an equation, the TFF circuits 9 receive, under a normal mode, control signals from a control circuit previously assembled in the chip and provide the control signals to the macroblocks to let the macroblocks execute predetermined operations. Under a test mode, the TFF circuits 9 receive control signals from the outside of the chip and provide the control signals to the macroblocks to let the macroblocks execute operations to be tested. The latch circuits 3 of the macroblock 1, the macroblock 4, the output buffers 5 of the macroblocks 1 and 4 and the I/O buffers 6 are connected to bus line 2 and enabled or disabled by-the circuits 10, respectively. The circuit 10 is similar to the circuit 9 and, therefore, it is also called the TFF circuit. An output of each of the TFF circuits 9 and 10 is determined according to the following equation in which the TFF circuits 9 and 10 are generally distinguished from each other with the use of a subscript "i" (or "j"): EQU (OUTPUT)i=MBT*SGN+MBT*ENi*Qi
In the expression, the MBT is an operation mode selection signal. When the signal MBT is 0, a normal mode is selected. When the signal MBT is 1, a test mode is selected.
The SGN is a control signal for the normal mode.
The ENi are enable signals for the respective TFF circuits 9 and 10 and generated by an enable signal generating circuit (TGEN) 11. The enable signal generating circuit 11 receives a sequence control signal TEN that controls a test sequence. The enable signals ENi to the TFF circuits are not necessarily different from each other. Depending on operations necessary for the test, a common enable signal may be used for a plurality of the TFF circuits.
The Qi are outputs of flip-flop circuits (FFs) arranged in the TFF circuits 9 and 10. The flip-flop circuits of the TFF circuits 9 and 10 are arranged to form a series scan chain. A Q-output of each of the flip-flop circuits is set to 0 or 1 in synchronism with a clock. When the signal MBT changes from 0 to 1, a logical value held at the Q-output at the time of this change of signal MBT is kept, while the signal MBT is maintained at 1.
If the signal ENi is applied to the TFF circuit 10(i) during a test period (with the Q-outputs of respective flip-flops having been set and with the signal MBT being 1) and if a signal Qi (fixed) of the flip-flop circuit of the TFF circuit 10(i) is 1, a circuit connected to the TFF circuit in question is enabled. If a signal ENi is applied to the TFF circuit 9(j) of the macroblocks 1 and 4, a control signal held in the TFF circuit 9(j) is applied to the macroblocks 1 and 4.
With the arrangement mentioned in the above, external data can be inputted to the macroblocks 1 and 4, and data can be read out of the macroblocks 1 and 4 to the outside to directly test operation of the macroblocks 1 and 4.
However, the conventional test circuit of this sort has problems.
For inputting control signals to the respective macroblocks, the TFF circuits shall be arranged for the macroblocks, respectively. This may require particular areas and wiring. Therefore, it is quite disadvantageous to install a conventional test circuit in an integrated circuit.
Moreover, it is impossible to test the macroblocks under operating conditions that are completely the same as actual operating conditions realized by control signals issued by a microdecoder.